1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a split gate flash memory cell and a manufacturing method thereof.
2. Description of Related Art
A flash memory device provides the property of multiple entries, retrievals and erasures of data. Moreover, the stored information is retained even electrical power is interrupted. As a result, a non-volatile memory device is widely used in personal computers and electronic systems.
A typical flash memory device employs doped polysilicon to fabricate the floating gate and the control gate. Further, a dielectric layer is used to isolate the floating gate from the control gate, while the floating gate and the substrate are isolated from each other by a tunneling oxide layer. When a flash memory device performs the write/erase operation of information, proper biases are applied to the control gate and the source/drain regions to inject electrons into or to discharge electrons from the floating gate. Further, the reading of information from a flash memory device is achieved by applying a working voltage to the control gate. The conductive state of the floating gate influences the opening/closing of the channel, wherein the opening/closing of the channel can be interpreted as the binary value of either “0” or “1”.
During the erasure of information of the above flash memory device, the amount of electrons being discharged is difficult to control. Consequently, over-erase is resulted when an excessive amount of the electrons are discharged from the floating gate, leaving the floating gate with positive charges. When the over-erase phenomenon is serious, a channel current flow is induced under the floating gate even no working voltage is applied to the control gate, leading to an erroneous interpretation of the data.
To resolve the over-erase problem, many flash memory devices uses the split gate design. The split gate design, in addition to the control gate and the floating gate, further includes a selective gate (or an erase gate) disposed on the sidewalls of the control gate and the floating gate and above the substrate, wherein the split gate is isolated from the control gate, the floating gate and the substrate with a dielectric layer. Accordingly, as the over-erase phenomenon becomes serious, in which the channel under the floating gate maintains opened even under no working voltage is being applied to the control gate, the channel under the selective gate can maintain closed to obviate a current flow between the source region and the drain region. An erroneous interpretation of the stored information can thus be precluded. Since a split gate structure demands a larger split gate region and thus a larger memory cell, the dimension of a split gate memory cell is larger than that of a stacked gate flash memory cell. Further increase of the device integration is thereby prohibited.
Normally, as the gate couple ratio (GCR) between the floating gate and the control gate becomes larger, the working voltage required for the operation diminishes. To raise the gate couple ratio includes increasing the dielectric capacity of the gate dielectric layer or reducing the dielectric capacity of the tunneling oxide layer, wherein increasing the dielectric capacity of the gate dielectric layer includes increasing the area in between the control gate layer and the floating gate. However, in a conventional split gate structure, the control gate and the floating gate form a stacked structure. The area between the control gate and the floating gate can not be further increased. As a result, the gate coupling ratio and the integration of devices can not be increased.